1. Field of the Invention
The present invention relates to a voltage supply to a semiconductor memory, and more particularly to a voltage supply to a semiconductor memory, which can supply a regulated voltage to the memory.
2. Background of the Related Art
In erasure of a flash EEPROM cell array, a negative voltage supply provides a negative regulated voltage to a control gate through a wordline. FIG. 1 illustrates a block diagram showing a related art negative voltage supply, FIG. 2 illustrates a voltage regulating circuit in the related art negative voltage supply, and FIG. 3 illustrates Vcc vs. VNEG in the negative voltage supply.
Referring to FIG. 1, the related art negative voltage supply is provided with a charge pump circuit 1 for providing a constant voltage, a clock circuit 2 for applying clock pulses to the charge pump circuit 1, a voltage regulating circuit 3 for monitoring (the voltage from the charge pump circuit 1 to keep enabling the charge pump circuit 1 until a desired voltage is provided and to generating a disenable signal if a voltage higher than the desired voltage to stop the charge pump.
Referring to FIG. 2, the voltage regulating circuit 3 is provided with a first, and a second current mirrors each for receiving an erasure operation signal and a driving voltage V.sub.DD, a reference voltage V.sub.REF supply unit 13 for receiving the erasure operation signal, the driving voltage V.sub.DD and the reference voltage V.sub.REF, a voltage distribution unit 14, a forwarding unit 15 for receiving the driving voltage V.sub.DD and forwarding a voltage VNEG of the negative voltage supply, and a first, and a second NMOS's N1 and N2 for receiving a high voltage signal HVON and an X address selecting signal XALLSEL. The first, and second current mirrors 11 and 12 are applied of a node A voltage in common. The node A is a cross point of the a common input line to the first, and second current mirrors 11 and 12 and a drain of the first NMOS N1. The reference voltage V.sub.REF supply unit 13 is provided with a first, and a second reference voltage suppliers 16 and 17 and a third, and a fourth NMOS N3 and N4 each having a grounded source. The first reference voltage supplier 16 is provided with a third PMOS P3 having a drain connected to the driving voltage V.sub.DD and a gate connected to an inverted erasing operation signal, and a plurality of resistors connected in series between a source of the third PMOS P3 and a ground voltage Vss, for providing a first reference voltage to one input terminal on the first current mirror 11. The second reference voltage supplier 17 is provided with a fifth NMOS N5, a first capacitor C1, and a second grounded capacitor C2, for providing a second reference voltage, outputs from the first, and second capacitors C1 and C2, to one input terminal on the second current mirror 12. The fifth NMOS N5 has a gate connected to the erasing operation signal through four first inverters i1, a source connected to the reference voltage V.sub.REF, and a drain connected to a drain of the third NMOS N3 and the first capacitor C1. The first capacitor C2 is connected to the first capacitor C1. A gate of the third NMOS N3 is connected to the fourth NMOS N4, and a drain of the fourth NMOS N4 is connected to the second reference voltage. The voltage distribution unit 14 is provided with a third capacitor connected to the common input to the first, and second current mirrors 11 and 12, a third capacitor C3 connected to the VNEG, and a fourth capacitor C4 having one terminal connected to the common input to the first and second current mirror 11 and 12 and the other terminal grounded. The forwarding unit 15 is provided with a first, and a second PMOS's P1 and P2. The first PMOS P1 has a drain connected to the driving voltage V.sub.DD, a source connected to the VNEG, and a gate connected to an output terminal to the first current mirror 11 through a second inverter i2. The second PMOS P2 has a drain connected to the driving voltage V.sub.DD, a source connected to VNEG, and a gate connected to an output terminal on the second current mirror 12 through the third inverter i3. And, the first NMOS N1 has a drain connected to the node A, a source connected to a source of the second NMOS N2, and a gate to HVON through the fourth inverter i4. And, the second NMOS N2 has a drain connected to the V.sub.REF, and a gate connected to XALLSEL through the fifth inverter i5.
The operation of the aforementioned voltage regulating circuit in the related art negative voltage supply will be explained.
When an erasing operation of the flash EEPROM cell array is started under a state the node A is precharged of a reference voltage V.sub.REF as the first, and second NMOS's N1 and N2 are turned-on because the HVON and XALLSEL are at low, the negative charge pump circuit 1 comes into operation, to increase the VNEG gradually and the voltage regulating circuit 3 is applied of the erasing operation signal. Upon application of the erasing operation signal to the voltage regulating circuit 3, the first, and second current mirrors 11 and 12 and the fifth NMOS N5 are turned on, bringing the voltage regulating circuit 3 into operation. In this instance, since HVON and XALLSEL are transited to high, turning off the first, and second NMOS N1 and N2, the node A is, not connected to the reference voltage reference V.sub.REF, but becomes a coupling voltage through the third, and fourth capacitors C3 and C4 in the voltage distribution unit 14 due to VNEG. And, the first, and second current mirrors 11 and 12 respectively compare the first and second reference voltages to a node A voltage. Since an operative relation of the first current mirror 11, the second inverter i2, and the first PMOS P1 is the same with an operative relation of the second current mirror 12, the third inverter i3, and the second PMOS P2, the operative relation on the first current mirror 11, the second inverter i2, and the first PMOS P1 will only be explained. If VNEG is increased higher than a preset reference, i.e., the node A voltage is lower than the first reference voltage, the first current mirror 11 provides a high signal, a control signal, to the first PMOS P1 through the second inverter i2, to turn on the first PMOS P1. Upon turning on the first PMOS P1, V.sub.DD is applied to VNEG, decreasing the VNEG. The VNEG is kept decreased due to the application of V.sub.DD until VNEG comes below the preset reference, i.e., the node A voltage is higher than reference voltage V.sub.REF, when the first current mirror 11 provides a low signal, a control signal, to the first PMOS P1 through the second inverter i2, turning off the first PMOS P1. Upon turning off the first PMOS P1, V.sub.DD can not be applied to VNEG, increasing the VNEG, again. In this instance, because an amount of charge supplied from the negative charge pump 1 differs significantly depending on power source voltage Vcc, the higher the power source voltage, the greater the current supply capability of the charge pump, also with a change of the coupling voltage. As the node A voltage is changed according to the change of the coupling voltage, as shown in FIG. 3, VNEG from the related art negative voltage supply is changed depending on power supply voltage Vcc.
Accordingly, the related art voltage supply to a semiconductor memory has a problem in that an erasing operation of a flash EEPROM cell array is not stable due to changes of VNEG depending on Vcc and in that a size of the voltage regulating circuit is large because of the use of the first, and second reference voltage suppliers and two current mirrors on the same time in which a capacitance distibutor and a resistance distributor are used for reducing a variation of the VNEG.